Volume 5, Issue 1, June 2019, Page: 13-18
The Design of Three Phase Programmable Testing Power Based on CPLD_DSP
Li Hui, Automated Institute, Huaiyin Institute of Technology, Huaian, China
Li Jing, Automated Institute, Huaiyin Institute of Technology, Huaian, China
Received: Aug. 3, 2019;       Accepted: Aug. 19, 2019;       Published: Sep. 3, 2019
DOI: 10.11648/j.awcn.20190501.12      View  691      Downloads  89
A design of three phases programmable testing power program-controlled based on CPLD_DSP was introduced in the paper. RAM was driven and six DDS were generated in CPLD. RAM was driven and six DDS (three voltage signal and three current signal) were generated in CPLD. The six DDS signal was used as based signal of testing power. CPLD was programmed to control serial D/A chip named LTC1595B to adjust the value of voltage and current. Voltage signal and current signal were collected and computed and closed loop by DSP. After testing, the output frequency resolution of the system achieved 0.001Hz.The voltage and current control precision achieved 0.02%.
Testing Power, CPLD, DDS, Output Precision
To cite this article
Li Hui, Li Jing, The Design of Three Phase Programmable Testing Power Based on CPLD_DSP, Advances in Wireless Communications and Networks. Vol. 5, No. 1, 2019, pp. 13-18. doi: 10.11648/j.awcn.20190501.12
Copyright © 2019 Authors retain the copyright of this article.
This article is an open access article distributed under the Creative Commons Attribution License (http://creativecommons.org/licenses/by/4.0/) which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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